1. Field of the Invention
Various embodiments of the present disclosure relate to a substrate used for a semiconductor package and a semiconductor package including the same.
2. Description of the Related Art
With high performance of electric/electronic products and reduction in size and weight of electronic devices, it has become important to reduce the thickness of packages and increase the density of packages. With the increase in memory capacity of computers, notebooks, and mobile phones, the capacity of chips such as large-capacity RAM and flash memory has increased, but the size of packages has decreased. In order to implement such packages, research has been conducted according to the trend where the size of packages is reduced. Furthermore, various techniques for mounting a larger number of packages in a substrate having a limited area are being researched.
In order to reduce the size of a package, a technique which is capable of reducing the size and thickness of a package while using chips having the same memory capacity has been proposed, and the package is typically referred to as a flip chip package. The flip chip package has a structure in which a semiconductor chip and a printed circuit board (PCB) are electrically coupled through a bump formed on a bonding pad of a chip. Since the transmission of electrical signals between the chip and the PCB is performed only by the bump, the flip chip package has a very short signal transmission path. Therefore, the flip chip package technique is known as a packaging technique suitable for high-speed devices.
In the flip chip package, a semiconductor chip is directly coupled to a package substrate through a bump formed on a bonding pad thereof, and the package substrate is coupled to a system substrate through a solder ball formed on the opposite surface of the package substrate having the semiconductor chip mounted thereon. Therefore, two or more metal layers such as electrodes for coupling the semiconductor chip and the package substrate and electrodes for coupling the system substrate and the package substrate are required to implement the flip chip package. Furthermore, such metal layers are coupled through conductive vias formed in the substrate.
However, when pluralities of metal layers are coupled through conductive vias, the metal layers may be discontinuously coupled. The discontinuous coupling between the metal layers for signal transmission has no problem when DC current for power supply or a signal operating at a relatively low frequency is transmitted to a semiconductor chip. However, the discontinuous coupling may cause impedance mismatch when a signal operating at a high frequency is transmitted.
FIGS. 1A and 1B are graphs showing an insertion loss and a return loss for a signal frequency, respectively.
Referring to FIG. 1A (i.e., y-axis is LOSS and x-axis is FREQUENCY), when a substrate is not used, there is no signal loss, which is indicated by a thin line. However, when the substrate is used, a rapid signal transmission loss occurs in a specific frequency band, which is indicated by a thick line.
Referring to FIG. 1B (i.e., y-axis is LOSS and x-axis is FREQUENCY), when a substrate is not used, there is no signal loss, which is indicated by a thin line. However, when the substrate is used, a rapid signal transmission loss occurs in a specific frequency band, which is indicated by a thick line.
Such a loss may be caused by impedance mismatch of transmission lines. Furthermore, when a semiconductor chip and a system substrate is coupled through conductive vias, a signal transmission path between the semiconductor chip and the system substrate may be lengthened. This may cause signal delay.